Part 6 : Reference Clock Jitter and Data Jitter 1 Reference Clock Jitter and Data Jitter

Reference clock jitter sets the ultimate limit on the bit error ratio of a serial data system. The traditional techniques for quantifying jitter on clock signals don’t help system designers estimate the clock’s contribution to the total jitter defined at a bit error ratio. New techniques are being introduced to model how transmitters and receivers use reference clocks so that the system RJ and DJ attributable to the reference clock can be measured and maximums specified. This installment of Jitter 360 shows how reference clock jitter affects data jitter at each point in the system and describes techniques for its analysis. We’ve seen that the different types of jitter are predominantly generated in specific components of the network. For example, Data Dependent Jitter (DDJ) is generated in the transmission path; Periodic Jitter (PJ) is caused by electromagnetic interference of one sort or another; and Random Jitter (RJ) is caused by “the combination of a huge number of sources, each of very small magnitude” (lifted from Part 3 of this series, All About the Acronyms). Most of those very small RJ sources originate in the oscillator that drives the reference clock of the transmitter. As data rates get higher, jitter budgets get tighter, and we can no longer afford to lump jitter caused by the reference clock under “transmitter jitter.” As rates surpass 2 Gb/s more and more standards bodies are providing explicit specifications for reference clock jitter and the new specifications are not easily related to the numbers recorded on most data sheets. Figure 1 is a block diagram of a serial-data system. The four primary components are the transmitter, transmission path, receiver, and reference clock. The role of the reference clock is to define the timing of logic transitions at the transmitter and to provide a reference for setting the time-delay of the sampling point at the receiver. There are two types of clock systems. In embedded clock systems the only clock information available to the receiver is embedded in the data; in this case the dashed line in Figure 1 is not connected. In distributed clock systems, the dashed line in Figure 1 connects the reference clock to the receiver. Jitter 360° Knowledge Series Part 6: Reference Clock Jitter and Data Jitter 2 In this edition of Jitter 360, we’ll see how RJ is generated in oscillators, how reference clock jitter propagates onto data jitter, and we’ll have a look at how reference clocks can be evaluated in the emerging high rate serial-data standards. Figure 1: Serial-data straw diagram emphasizing the role of the reference clock. Oscillators The oscillator, whether based on an inexpensive LC circuit or a crystal, provides the periodic structure on which a digital system is based. The parameters used to describe oscillators are easily defined by using the example of an LRC circuit shown, Figure 2. Figure 2: A simple oscillator and typical parameters. The highest quality oscillators are based on crystals. Crystal oscillators, Figure 3, are composed of media, like quartz, which have easily excited piezoelectric properties. Stable oscillations are generated through a simple sequence based on the fact that any excitation will have its greatest response at the crystal’s resonant frequency. First, random noise is applied to the crystal. The response is amplified and a feedback loop generates subsequent crystal response that builds at the resonant frequency. The output ( ) 1 2 1 2 LC L R LC R ≈ − = ω